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INTEGRATED CIRCUITS
DATA SHEET
TDA9160 PAL/NTSC/SECAM decoder/sync processor
Preliminary specification File under Integrated Circuits, IC02 December 1991
Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
FEATURES * Multistandard PAL, NTSC and SECAM * I2C-bus controlled * I2C-bus addresses can be selected by hardware * Alignment free * Few external components * Designed for use with baseband delay lines * Integrated video filters * Horizontal and vertical drive output * East-West correction drive output * Two CVBS inputs * S-VHS input * Vertical divider system * HA synchronization pulse * Two level sandcastle pulse GENERAL DESCRIPTION The TDA9160 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/processor. The device contains horizontal and vertical drive outputs and an east-west correction drive circuit. The TDA9160 has been designed for use with baseband chrominance delay lines and DC-coupled vertical and east-west output circuits. The device has three inputs, two for CVBS and one for S-VHS. The main signal is available at the luminance and colour difference outputs and, also, at the TXT output (unprocessed). The signal at the PIP output can be selected independently from the main signal. The circuit provides a drive pulse for the horizontal output stage, a differential sawtooth current for the vertical output stage and an east-west
TDA9160
drive current for the EW output stage. These signals can be used to provide geometry correction of the picture. A two level sandcastle pulse and an HA pulse are made available for synchronization purposes .The I2C-bus address of the TDA9160 can be programmed by hardware.
Fig.1 Block diagram.
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
QUICK REFERENCE DATA SYMBOL VCC ICC V24,26(p-p) V23(p-p) V22(p-p) V1(p-p) V25(p-p) V2(p-p) V2(p-p) V3(p-p) V3(p-p) V10 I15,16(p-p) I18 I17 V6 V6 supply current CVBS input voltage (peak-to-peak value) S-VHS luminance input voltage (peak-to-peak value) S-VHS chrominance burst input voltage (peak-to-peak value) luminance output voltage (peak-to-peak value) teletext output voltage (peak-to-peak value) chrominance output voltage -(R-Y) (peak-to-peak value) chrominance output voltage -(R-Y) (peak-to-peak value) chrominance output voltage -(B-Y) (peak-to-peak value) chrominance output voltage -(B-Y) (peak-to-peak value) HA output voltage vertical drive output current (peak-to-peak value) horizontal drive output current EW drive output current sandcastle clamping voltage level sandcastle blanking voltage level PAL/NTSC SECAM PAL/NTSC SECAM PARAMETER positive supply voltage CONDITIONS MIN. TYP. 7.2 - - - - - - - - - - - - - - - - 8.0 50 1.0 1.0 0.3 0.45 1.0 525 1.05 665 1.33 5.0 1 - - 4.5 2.5
TDA9160
MAX. 8.8 - - - - - - - - - - - - 10 0.9 - -
UNIT V mA V V V V V mV V mV V V mA mA mA V V
ORDERING INFORMATION EXTENDED TYPE NUMBER TDA9160 Note 1. SOT232-1; 1996 December 2. PACKAGE PINS 32 PIN POSITION SDIL MATERIAL plastic CODE SOT232(1)
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
PINNING SYMBOL Y -(R-Y) -(B-Y) SCL SDA SC VCC DEC DGND HA Vsaw Iref AGND1 EHT/PROT VOUTA VOUTB EWOUT HOUT HFB PIP HPLL SVHSC SVHSY CVBS2 TXT CVBS1 AGND2 FILTref PLL XTAL Fig.2 Pin configuration. XTAL2 SECref PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA9160
DESCRIPTION luminance output chrominance output chrominance output serial clock input serial data input/output sandcastle output positive supply input positive supply decoupling digital ground horizontal acquisition synchronization pulse vertical sawtooth input current reference analog ground EHT tracking and over-voltage protection vertical drive output A vertical drive output B east-west drive output horizontal drive output horizontal flyback input picture-in-picture output horizontal PLL filter S-VHS chrominance input S-VHS luminance input CVBS2 input teletext output CVBS1 input analog ground filter reference decoupling colour PLL filter reference crystal input second crystal input SECAM reference decoupling
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
FUNCTIONAL DESCRIPTION The TDA9160 is an controlled, alignment free PAL/NTSC/SECAM colour decoder/sync processor/deflection controller which has been designed for use with baseband chrominance delay lines. In the standard operating mode the I2C-bus address is 8A . If the TXT output is connected to the positive rail the address will change to 8E The standards which the TDA9160 can decode are dependent on the choice of external crystals. If a 4.4 MHz and a 3.6 MHz crystal are used then SECAM, PAL 4.4/3.6 and NTSC 4.4/3.6 can be decoded. If two 3.6 MHz crystals are used then only PAL 3.6 and NTSC 3.6 can be decoded. Which 3.6 MHz standards can be decoded is dependent on the exact frequencies of the crystal. In an application where not all standards are required only one crystal is sufficient (in this instance the crystal must be connected to the reference crystal input (pin 30)). If a 4.4 MHz crystal is used it must always be connected to pin 30. Both crystals are used to provide a reference for the filters and the horizontal PLL, however, only the reference crystal is used to provide a reference for the SECAM demodulator. To enable the calibrating circuits to be adjusted exactly two bits from the I2C-bus address are used to indicate which crystals are connected to the IC. The standard identification circuit is a digital circuit without external components; the search loop is illustrated in Fig.3. The decoder (via the I2C-bus) can be forced to decode either SECAM or PAL/NTSC (but not PAL or NTSC). Crystal selection can also be forced. Information, concerning which I2C-bus standard and which crystal have been selected and whether the colour killer is ON or OFF is provided by the read out. Using the forced-mode does not affect the search loop, it does, however, prevent the decoder from reaching or staying in an unwanted state. The identification circuit skips impossible standards (e.g. SECAM when no 4.4 MHz crystal is fitted) and illegal standards (e.g. forced mode). To reduce the risk of wrong identification PAL has priority over SECAM (only line identification is used for SECAM). The TDA9160 has two CVBS inputs and one S-VHS input which can be selected via the I2C-bus. The input selector can also be switched to enable CVBS2 to be processed, providing that there is no S-VHS signal present at the input. If the input selector is set to CVBS2 it will switch to S-VHS if an S-VHS sync pulse is detected at the luminance input. The S-VHS detector output can be read via the I2C-bus. If the voltage at either the S-VHS luminance or the chrominance input (pins 22 and 23) exceeds +5.5 V the IC will revert to test mode. The TDA9160 also provides outputs for picture-in-picture and teletext (PIP pin 20 and TXT pin 25). The decoder input signal can be switched directly to the TXT output. The PIP output signal can be selected independently from the TXT output. If S-VHS is selected at the TXT output only the luminance signal will be present; if S-VHS is selected at the PIP output then the luminance and chrominance signals will be added. All filters, including the luminance delay line, are an integral part of the IC. The filters are gyrator-capacitor type filters. The resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the
TDA9160
SECAM Cloche filter during the vertical flyback time. The remaining filters and the delay line are matched to this filter. The filters can be switched to either 4.43 MHz, 4.28 MHz or 3.58 MHz irrespective of the frequency of the active crystal. The switching is controlled by the identification circuit. The S-VHS luminance signal does not pass through the notch filter to preserve bandwidth. The luminance delay line delivers the Y signal to the output 40 ns after the -(R-Y) and -(B-Y) signals. This compensates for the delay of the external chrominance delay lines. The PAL/NTSC demodulator employs an oscillator that can operate with either crystal (3.6 or 4.4 MHz). If the I2C-bus indicates that only one crystal is connected it will always connect to the crystal at the reference input (pin 30). The Hue signal, which is adjustable via the I2C-bus, is gated during the burst for NTSC signals. The SECAM demodulator is an auto-calibrating PLL demodulator which has two references. The reference crystal, to force the PLL to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical flyback period, when the reference crystal is active. When the second crystal is active the VCO is not calibrated. During this time the frequency of the VCO is kept constant by applying a constant voltage to its control input. If the reference crystal is not 4.4 MHz the decoder will not produce the correct SECAM signals. The main part of the sync circuit is a 432 x fH (6.75 MHz) oscillator the frequency of which is divided by 432
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
to lock the phase 1 loop to the incoming signal. The time constant of the loop can be forced by the I2C-bus (fast or slow). If required the IC can select the time constant, depending on the noise content of the input signal and whether the loop is phase locked or not (medium or slow). The free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal. When a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency greater than 6.75 MHz to protect the horizontal output transistor. The oscillator frequency is reset to 6.75 MHz when the crystal indication bits have been loaded into the IC. To ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. Subaddress 00 contains the crystal indication bits, when subaddress 01 is received the line oscillator calibration will be initiated. The calibration is terminated when the oscillator frequency reaches 6.75 MHz. The oscillator is again calibrated when an out-of-lock condition with the input signal is realised by the coincidence detector. Again the calibration will be terminated when the oscillator frequency reaches 6.75 MHz. The phase 1 loop can be opened using the I2C-bus. This is to facilitate On Screen Display (OSD) information. If there is no input signal or a very noisy input signal the phase 1 loop can be opened to provide a stable line frequency and thus a stable picture. The sync part provides an HA pulse that is coupled to the processed CVBS signal. The horizontal drive signal can be switched off via the I2C-bus (standby mode). The horizontal drive is also switched off when the over-voltage December 1991 protection circuit trips or when a POR is detected. Should either of these two conditions occur the IC will return to the normal operating mode when the appropriate command is received via the I2C-bus. The duty cycle of the horizontal drive signal is increased from 2%, at start-up, to a constant value of 55% in approximately 300 lines. The two-level sandcastle pulse provides a combined horizontal and vertical blanking signal and a clamping pulse coupled to the display section of the TV. The vertical sawtooth generator drives the geometry processing circuits which provide control for the horizontal shift, EW width, EW parabola/width ratio, EW corner/parabola ratio, trapezium correction, vertical slope, vertical shift, vertical amplitude and the S-correction. All of these control functions can be set via the I2C-bus. The geometry processor has a differential current output for the vertical drive signal and a single-ended output for the EW drive. Both the vertical drive and the EW drive outputs can be modulated for EHT compensation. The EHT compensation pin (pin 14) can also be used for over-voltage protection. De-interlace of the vertical output can be set via the I2C-bus. The vertical divider system has a fully integrated vertical sync separator. The divider can accommodate both 50 and 60 Hz systems; it can either locate the field frequency automatically or it can be forced to the desired system via the I2C-bus. A block diagram of the vertical divider system is illustrated in Fig.4. The divider system operates at 432 times the horizontal line frequency. The line counter receives enable pulses at twice the line frequency, thereby counting two lines per pulse. A state diagram of the controller is illustrated in Fig.5. Because it is
TDA9160
symmetrical only the right hand part will be described. Depending on the previously found field frequency, the controller will be in one of the 'count' states. When the line counter has counted 488 pulses (i.e. 244 lines of the video input signal) the controller will move to the next state depending on the output of the norm counter. This can be either NORM, NEAR-NORM or NO-NORM depending on the position of the vertical sync pulse in the previous fields. When the counter is in the NORM state it generates the vertical sync pulse (VSP) automatically and then, when the line counter is at LC = 626, moves to the WAIT state. In this condition it waits for the next pulse of the double line frequency signal and then moves to the COUNT state of the current field frequency. When the controller returns to the COUNT state the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal. When the controller is in the NEAR-NORM state it will move to the COUNT state if it detects the vertical sync pulse within the NEAR-NORM window (i.e. 622 < LC < 628). If no vertical sync pulse is detected, the controller will move back to the COUNT state when the line counter reaches LC = 628. The line counter will then be reset. When the controller is in the NO-NORM state it will move to the COUNT state when it detects a vertical sync pulse and reset the line counter. If a sync pulse is not detected before LC = 722 (if the phase loop is locked in forced mode) it will move to the COUNT state and reset the line counter. If the phase loop is not locked the controller will move back to the COUNT state when LC = 628. The forced mode option keeps the controller in either the left-hand side (60 Hz) or the
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
right-hand side (50 Hz) of the state diagram. Figure 6 illustrates the state diagram of the 'norm' counter which is an up/down counter that counts up if it finds a vertical sync pulse within the selected window. In the NEAR-NORM and NORM states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. This procedure prevents the system from staying in the NEAR-NORM or NORM state if the vertical sync pulse is correct in the first field and incorrect in the second field. If no vertical sync pulse is found in the selected window this will always result in a down pulse for the 'norm' counter. Figure 7 illustrates the timing of the display sandcastle (DSC) and the reset pulse of the vertical sawtooth with respect to the input signal I2C-bus protocol
TDA9160
If the TXT output is connected to the positive supply the address will change from 8A to 8E. Valid subaddresses = 00 to 0F Auto-increment mode available for subaddresses. Subaddress 00 must always be sent before subaddress 01 in order to protect the horizontal output transistor.
Table 1 A6 1 Table 2
Slave address (8A) A5 0 Inputs MSB INA FORF - - - - - - - - - SBL Outputs POR FSI STS SL PROT SAK SBK FRQ INB FORS - - - - - - - - - - INC DL HU5 HS5 EW5 PW5 CP5 TC5 VS5 VA5 SC5 VSH5 IND STB HU4 HS4 EW4 PW4 CP4 TC4 CS4 VA4 SC4 VSH4 FOA POC HU3 HS3 EW3 PW3 CP3 TC3 VS3 VA3 SC3 VSH3 FOB FM HU2 HS2 EW2 PW2 CP2 TC2 VS2 VA2 SC2 VSH2 XA SAF HU1 HS1 EW1 PW1 CP1 TC1 VS1 VA1 SC1 VSH1 LSB XB FRQF HU0 HS0 EW0 PW0 CP0 TC0 VS0 VA0 SC0 VSH0 A4 0 A3 0 A2 1 A1 X A0 1 R/W X
SUBADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B Table 3
ADDRESS
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
TDA9160
Fig.3 Search loop of the identification circuit.
Fig.4 Block diagram of the vertical divider system.
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
TDA9160
Fig.5 State diagram of the vertical divider system.
Fig.6 State diagram of the `norm' counter.
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
TDA9160
Fig.7 Field timing diagram.
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
INPUT SIGNALS Table 4 INA 0 0 1 1 Table 6 FOA 0 0 1 Source select 1 INB 0 1 0 1 DECODER AND TXT CVBS1 CVBS2 S-VHS S-VHS (CVBS2) Table 5 INC 0 0 1 1 Table 7 MODE auto slow fast XA 0 0 1 1 Table 8 FORF 0 0 1 1 Forced field frequency FORS 0 1 0 1 auto 60 Hz 50 Hz auto FIELD FREQUENCY 0 1 Table 9 DL interlace de-interlace Source select 2 IND 0 1 0 1
TDA9160
DECODER AND TXT CVBS1 CVBS2 S-VHS S-VHS (CVBS2)
Phase time constant FOB 0 1 -
XTAL indication XB 0 1 0 1 Interlace CONDITION CRYSTAL 2 x 3.6 MHz 1 x 3.6 MHz 1 x 4.4 MHz 3.6 and 4.4 MHz
Table 10 Standby STB 0 1 standby normal mode CONDITION
Table 11 Phase loop control POC 0 1 CONDITION phi one loop closed phi one loop open
Table 12 Forced standard ADD FM SAF FRQF 0 1 0 1 0 1 Note to table 12 1. If XA and XB indicate that only one crystal is connected to the IC and FM and FRQF force it to use the second crystal the colour will be switched off. LOGIC CONDITION auto search forced mode PAL/NTSC SECAM second crystal reference crystal
Table 13 Service blanking SBL 0 1 CONDITION service blanking OFF service blanking ON
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
Table 14 Other input signals FUNCTION hue horizontal shift EW width EW parabola/width EW corner/parabola EW trapezium vertical slope vertical amplitude S correction vertical shift Table 15 Standard read-out SAK 0 0 0 0 1 1 1 1 SBK 0 0 1 1 0 0 1 1 FRQ 0 1 0 1 0 1 0 1 PAL, second crystal PAL, reference crystal NTSC, second crystal NTSC, reference crystal not used SECAM, reference crystal colour off colour off STANDARD ADDRESS HU5 to HU0 HS5 to HS0 EW5 to EW0 PW5 to PW0 CP5 to CP0 TC5 to TC0 VS5 to VS0 VA5 to VA0 SC5 to SC0 VSH5 to VSH0 000000 = -45 111111 = +45 000000 = -2.2 s 111111 = +2.2 s 000000 = 80% 111111 = 100% 000000 = 0% 111111 = 24% 000000 = 0% 111111 = -44% 000000 = -4% 111111 = +4% 000000 = -14% 111111 = +14% 000000 = -80% 111111 = +120% 000000 = 0% 111111 = 20% 000000 = -4% 111111 = +4% DIGITAL NUMBER
TDA9160
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PAL/NTSC/SECAM decoder/sync processor
INPUT SIGNALS Table 16 Power-on-reset POR 0 1 normal mode power-down mode CONDITION
TDA9160
Table 17 Field frequency indication FSI 0 1 Table 18 S-VHS status STS 0 1 no signal at input signal at input CONDITION 50 Hz 60 Hz CONDITION
Table 19 Phase lock indication SL 0 1 not locked locked CONDITION
Table 20 Over-voltage protection PROT 0 1 no over-voltage detected over-voltage detected CONDITION
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
LIMITING VALUES In accordance with the Absolute Maximum System (IEC134) SYMBOL VCC ICC Ptot Tstg Tamb PARAMETER positive supply voltage supply current total power dissipation storage temperature range operating ambient temperature range CONDITIONS - - - -55 -10 MIN.
TDA9160
MAX. 8.8 70 - +150 +65
UNIT V mA W C C
THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient in free air THERMAL RESISTANCE t.b.f.
CHARACTERISTICS VCC = 8 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supply VCC ICC Ptot positive supply voltage supply current total power dissipation 7.2 - - 8.0 50 400 8.8 - - V mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Input switch CVBS1 AND CVBS2 INPUTS (PINS 26 AND 24) V26,24(p-p) ZI V23(p-p) ZI V22(p-p) ZI V1(p-p) ZO VO S/N SUPP input voltage (peak-to-peak value) input impedance - 60 - 60 - 60 - - - - 50 1.0 - 1.0 - 0.3 - 450 - 2.1 tbf - 1.43 - 1.43 - 1.43 - - 500 - - - V k
S-VHS Y INPUT (PIN 23) input voltage (peak-to-peak value) input impedance V k
S-VHS CHROMINANCE INPUT input voltage (peak-to-peak value) input impedance burst V k
LUMINANCE OUTPUT (PIN 1) output voltage (peak-to-peak value) output impedance top sync level signal-to-noise ratio suppression of unselected inputs 14 mV V dB dB
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
TDA9160
SYMBOL
PARAMETER
CONDITIONS - - TXT output PIP output f = 0 to 5 MHz; PIP output f = 0 to 5 MHz; TXT output - - 50 35
MIN.
TYP. -
MAX.
UNIT
TXT AND PIP OUTPUTS (PINS 25 AND 20) V20,25(p-p) ZO VO SUPP SUPP output voltage (peak-to-peak value) output impedance top sync level suppression of unselected inputs suppression of unselected inputs 1.0 - 1.8 2.8 - - V V V dB dB
500 - - - -
Bias generator V8 V12 VACC(p-p) CR TC ZI Vdep 2/3 digital supply voltage DC voltage - - 5.0 3.9 - - - tbf 1.0 1.5 tbf - 1.27 tbf - 2.0 2.0 1 - tbf - - V V
Subcarrier regeneration burst amplitude within ACC range (peak-to-peak value) catching range phase shift for 400 Hz deviation temperature coefficient of oscillator input impedance supply voltage dependency change of -(R-Y) and -(B-Y) signals over the ACC range ratio of -(R-Y) and -(B-Y) signals TC temperature coefficient of -(R-Y) and -(B-Y) amplitude spread of -(R-Y) and -(B-Y) ratio between standards V2 V3 B ZO Vdep output level of -(R-Y) during blanking output level of -(B-Y) during blanking bandwidth output impedance supply voltage dependency at -3 dB reference crystal input second crystal input Demodulators - - - -1 - - - - - 1 - - +1 - - - 500 - Hz/K dB V V MHz V dB note 1 25 500 - - - - - 500 - 5 - - - - mV Hz deg Hz/K k k V
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Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
TDA9160
SYMBOL
PARAMETER -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) crosstalk between -(R-Y) and -(B-Y) 8.8 MHz residue (peak-to-peak value) 7.2 MHz residue (peak-to-peak value) signal-to-noise ratio
CONDITIONS - - - both outputs both outputs - - 46 - 46
MIN.
TYP. - - -
MAX.
UNIT
PAL/NTSC DEMODULATOR V2(p-p) V3(p-p) V2,3(p-p) V2,3(p-p) S/N standard colour bar standard colour bar 525 665 tbf - - - - - - 1.05 1.33 - 43 - 85 3 4.0 - mV mV dB mV mV dB
15 20 - 50 - +45 - - 7 - 30 93 - 5.0 3
PAL DEMODULATOR VR(p-p) S/N V2(p-p) V3(p-p) fOS S/N Vres(p-p) fpole H/2 ripple (peak-to-peak value) signal-to-noise ratio mV dB
NTSC DEMODULATOR hue phase shift -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) black level offset signal-to-noise ratio 7.8 to 9.4 MHz residue (peak-to-peak value) pole frequency of deemphasis ratio of pole and zero frequency Vcal NL Filters Vtune td td fO tuning voltage 1.5 - - 3.0 6.0 - - V calibration voltage non linearity -45 standard colour bar standard colour bar - - - - - 77 - 3.0 - deg
SECAM DEMODULATOR mV mV kHz dB mV kHz
V %
Luminance delay delay time delay time PAL/NTSC/BW SECAM 430 480 ns ns
Luminance trap notch frequency fSC = 3.6 MHz fSC = 4.4 MHz SECAM S-VHS/BW; not active December 1991 16 3.53 4.37 4.23 3.58 4.43 4.29 3.63 4.49 4.35 MHz MHz MHz
Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
TDA9160
SYMBOL B
PARAMETER bandwidth at -3 dB
CONDITIONS fSC = 3.6 MHz fSC = 4.4 MHz SECAM - - - 26 - - - -
MIN.
TYP. 2.8 3.4 3.3 - 3.58 4.43 1.6 2 - - - - - - - -
MAX.
UNIT MHz MHz MHz dB
SUPP
subcarrier suppression
CHROMINANCE BANDPASS fres B Cloche filter fres B Sync input V22 td S/N H td sync pulse amplitude slicing level delay of sync pulse due to internal filter noise detector threshold level hysteresis delay between video signal and internally separated vertical sync pulse CVBS 1/2; S-VHS input 50 - 0.2 - - 12 300 50 0.3 20 3 18.5 600 - 0.4 - - 27 mV % s dB dB s resonant frequency bandwidth SECAM at -3 dB; SECAM 4.26 241 4.29 268 4.31 295 MHz kHz resonant frequency bandwidth at -3 dB fSC = 3.6 MHz fSC = 4.4 MHz fSC = 3.6 MHz fSC = 4.4 MHz MHz MHz MHz MHz
Horizontal section HA OUTPUT (PIN 10) VOH VOL Isink Isource tW td output voltage HIGH output voltage LOW sink current source current pulse width delay between middle of horizontal sync pulse and middle of HA frequency deviation when not locked supply voltage ripple rejection temperature coefficient catching range holding range static phase shift 32 clock cycles note 2 2.4 - 2 2 - 0.3 5.0 0.3 - - 4.7 0.45 5.5 0.6 - - - 0.6 V V mA mA s s
FIRST LOOP f SVRR TC fCR fHR - - - 625 - - - tbf tbf - - - 1.5 - - - 1400 0.1 % V Hz/C Hz Hz s/kHz
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PAL/NTSC/SECAM decoder/sync processor
TDA9160
SYMBOL SECOND LOOP tCR
PARAMETER
CONDITIONS
MIN. - -
TYP. - -
MAX.
UNIT s/s s
control sensitivity control range of the positive going edge of horizontal drive to flyback delay between second loop reference and mid-sync of processed video HS = 00; note 4
300 13.5
td
-
3
-
s
HORIZONTAL SHIFT SR horizontal shift range 63 steps -2.2 - - - - - - 10 - - - 55 +2.2 s mA %
HORIZONTAL DRIVE OUTPUT (PIN 18) R18 I18 output resistance output current duty cycle of output current HORIZONTAL FLYBACK INPUT (PIN 19) VHB V2 V19 ZI Soft start CR duty cycle control range soft start time Vertical section (note 3) VERTICAL OSCILLATOR ffr fLR LR free running frequency frequency locking range divider locking range divider ratio 628 - 43 488 - - f = 50 Hz; VS = 1F 63 steps - -14 50 - 625 - 64 722 - - - +14 Hz Hz 2 200 - 300 55 500 % lines switching level for horizontal blanking switching level for phase two loop maximum input voltage input impedance 0.3 3.8 - - - - VCC - V V V M on-state 50 10 -
VERTICAL SAWTOOTH (PIN 11) V11(p-p) Idis Icharge CR voltage amplitude level (peak-to-peak value) discharge current charge current set by external resistor vertical slope control range VS = 1F; C = 100 nF; R = 39 k 3.5 1 19 - V mA A %
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PAL/NTSC/SECAM decoder/sync processor
TDA9160
SYMBOL
PARAMETER
CONDITIONS - - 0
MIN.
TYP. - -
MAX.
UNIT
VERTICAL DRIVE OUTPUTS (PINS 15 AND 16) Idiff(p-p) I15,16 VO TR SMR V14 differential output current (peak-to-peak value) common mode current output voltage range VA = 1F 1 400 - - - 7.5 3.9 mA A V
4.0
EHT TRACKING AND OVER-VOLTAGE PROTECTION (PIN 14) tracking range scan modulation range sensitivity over-voltage protection detection level 1.2 -6 - - 2.8 +6 - - V % %/V V
DE-INTERLACE first field delay Sandcastle (pin 6) V6 Isink Vbl Isource Iext zero level sink current 0 0.5 0.5 - 2.5 - - 1.0 - 3.0 - 3 V mA - 0.5H -
HORIZONTAL AND VERTICAL BLANKING blanking voltage level source current external current required to force the output to the blanking level 2.0 0.5 1 V mA mA
CLAMPING PULSE Vclamp Isource tW clamping voltage level source current pulse width PAL (17 LLC pulses) SECAM (24 LLC pulses) td delay between mid sync of input and start of clamping pulse 4.0 0.5 - - 3.6 4.5 - 2.5 3.6 3.7 5.0 - - - 3.8 V mA s s s
Geometry processing (note 3) EW WIDTH CR Ieq VO IO control range equivalent EW output current EW output voltage range EW output current range 63 steps 100 0 1.0 0 - - - - 80 400 8.0 900 % A V A
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PAL/NTSC/SECAM decoder/sync processor
TDA9160
SYMBOL EW PARABOLA/WIDTH CR Ieq CR Ieq CR Ieq TR SMR Ieq CR Ieq
PARAMETER
CONDITIONS
MIN. - - - - - - - - -
TYP.
MAX.
UNIT
control range equivalent EW output current
63 steps EW = 3F
0 0 -44 -210 -4 -80 1.2 -6 +120 -
24 480
% A % A % A V % A %/V
EW CORNER/PARABOLA control range equivalent EW output current 63 steps EW = 3F; PW = 3F 0 0 +4 +80 2.8 +6 -120 - 120 112 1200
EW TRAPEZIUM control range equivalent EW output current 63 steps
EW EHT TRACKING tracking range scan modulation range equivalent output current sensitivity
-7.5 - - -
VERTICAL AMPLITUDE control range equivalent differential vertical drive output current 63 steps; SC = 00 63 steps; SC = 3F SC = 00 80 86 800 % % A
VERTICAL SHIFT CR Ieq control range equivalent differential vertical drive output current 63 steps -4 -40 - - +4 +40 % A
S CORRECTION CR control range 63 steps 0 - 20 %
Notes to the characteristics 1. All oscillator specifications are measured with the Philips crystal series 4322 143/144. The spurious response of the reference crystal must be less than -7 dB with respect to the fundamental frequency for a damping resistance of 1 k. The spurious response of the second crystal must be less than -7 dB with respect to the fundamental frequency for a damping resistance of 1.5 k. 2. This delay is caused by the low pass filter at the sync separator input. 3. All values are valid for a reference current of 100 A (RC = 39 k). 4. Valid for flyback pulse width of 12 s at the switching level of the phase 2 loop.
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
QUALITY SPECIFICATION Quality level according to URV 4-2-59/601. SYMBOL ESD PARAMETER protection circuit specification (note1) RANGE A 2000 100 1500 Test and application information EW output stage In order to obtain the correct tracking of the vertical and horizontal EHT correction, the EW output stage should be configured as illustrated in figure 8.
TDA9160
RANGE B 500 200 0 V
UNIT pF
Fig.8 Configuration of the EW output stage.
Note to Fig.8 Resistor Rew determines the gain of the EW output stage. Resistor Rc sets the reference current for both the vertical sawtooth generator and the geometry processor. The preferred value of Rc = 39 k results in a reference current of 100 A (Vref = 3.9 V). V scan The value of Rew is given in the following equation: R ew = R c x -------------------------------( 18 x V ref ) Example: If Vref = 3.9 k, Rc = 39 k and Vscan = 120 V then Rew = 68 k
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
Control ranges of geometry control parameters Typical case curves (Rc = 39 k; Csaw = 100 nF)
TDA9160
VA = 0, 31 and 63; VSH = 31; SC = 0
VA = 31; VS = 0, 31 and 63; VSH = 31; SC = 0
Fig.9 Control range of vertical amplitude.
Fig.10 Control range of vertical slope.
VA = 31; VSH = 0, 31 and 63; SC = 0
SC = 0, 31 and 63; VA = 31; VSH = 31. The picture height does not change with the setting of S correction for nominal setting of vertical amplitude (VA = 31).
Fig.11 Control range of vertical shift. December 1991 22
Fig.12 Control range of S correction.
Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
TDA9160
EW = 0, 31 and 63; PW = 31; CP = 31 EW = 0, 31 and 63; PW = 31; CP = 31
Fig.13 Control range of EW width.
Fig.14 Control range of EW parabola/width ratio.
CP = 0, 31 and 63; EW = 31; PW = 63
TC = 0, 31 and 63; EW = 31; PW = 31; CP = 0
Fig.15 Control range of EW corner/parabola ratio.
Fig.16 Control range of EW trapezium correction.
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
Adjustment of geometry control parameters The deflection processor of the TDA9160 offers nine control parameters for picture alignment: * S-correction, vertical amplitude, vertical slope and vertical shift for the vertical picture alignment * Horizontal shift, EW width, EW parabola/width, EW corner/parabola and EW trapezium correction for the horizontal picture alignment The required values for the settings of S-correction, EW parabola/width ratio and EW corner/parabola ratio are determined for a particular combination of picture tube type, vertical output stage and EW output stage. These parameters can be preset via the I2C-bus and do not require any additional adjustment. The remainder of the parameters are preset to the mid value of their control range (i.e. 1F), or to values that have obtained from previous TV set adjustments. After the vertical S-correction has been preset the vertical picture alignment could, in theory, be completed by positioning the top of the picture using the vertical amplitude adjustment and the bottom of the picture using the vertical slope adjustment (see note). It can be shown, however, that without compensation offsets in the external vertical output stage or in the picture tube would result in a certain linearity error especially with picture tubes that need large S-correction. The total linearity error is in first order approximation proportional to the offset and to the square of the required S-correction. A vertical shift control is available for offset compensation. For adjustment of the vertical shift, independent of the vertical slope, a special vertical shift alignment is provided. This mode is entered by setting the SBL bit HIGH. In this mode the -(R-Y) and -(B-Y) outputs are blanked during the second half of the picture. The first line in which the colours are blanked must be positioned in the middle of the screen. The necessity to use the vertical shift alignment depends on the expected offsets in the vertical output stage and picture tube, on the required value of the S-correction and on the demands upon the vertical linearity. If the vertical shift alignment is not used
TDA9160
VSH should be set to its mid value (i.e. VSH = 1F). The actual factory adjustments of the picture consist of the following steps: * The vertical shift is adjusted as previously described (if required). * The top of the picture is positioned by adjusting the vertical amplitude and the bottom of the picture by adjusting the vertical slope * The picture is positioned in the horizontal direction by adjusting the EW width and horizontal shift * The left and right hand sides of the picture are aligned in parallel by adjusting the EW trapezium correction (if required). Note The value of the vertical slope determines the charge current of the vertical sawtooth capacitor (Csaw as shown in Fig.8) and thus the amplitude of the sawtooth voltage at pin 11. This voltage serves as the input voltage for the geometry processor. Consequently the setting of the vertical slope will affect both the vertical and EW output currents.
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December 1991 25 Fig.17 Application diagram. Notes to figure 17 1. Pins 31 and 32 are sensitive to leakage current. 2. The analog and digital ground currents should be well separated. 3. The decoupling capacitor connected between pins 8 and 9 must be placed as close to the IC as possible.
Philips Semiconductors Preliminary specification
PAL/NTSC/SECAM decoder/sync processor TDA9160
Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
TDA9160
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
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Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM decoder/sync processor
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9160
with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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